1. Field of the Invention
The present invention generally relates to integrated circuit fabrication processes and, in particular, to an integrated circuit process for forming a bipolar transistor having extrinsic base regions.
2. Description of the related Art
In the manufacture of integrated circuits, improvements in the state of the art in process techniques allow the fabrication of devices which have many more components on the same size die. At the same time that either the number of components is increased or the die size is reduced, it is necessary to reduce defects in order to provide a high manufacturing yield of operationally acceptable die on each wafer. As more and more components are constructed on each die, the increased device density should not result in any loss of manufacturing effectiveness. Preferably, performance and reliability would actually be improved in each generation despite the problems inherent in shrinkage.
For example, self-alignment process techniques, i.e., the use of one region or layer of a device as a mask to form another region, can improve the performance, reliability and yield factors.
Reducing the size of each component has other beneficial results. Parasitic capacitive effects can be minimized by lateral reduction of device regions. Vertical scaling, such as in the form of shallower junctions, and reduced base thicknesses enhance switching times, provide higher base-collector breakdown voltages, and prevent two-dimensional beta degradation. Therefore, a prime objective of integrated circuit fabrication technology is to develop process techniques to create layouts which are adaptable to shrinkage in both the lateral and vertical dimensions.
In bipolar circuit technology, improvement of individual transistor performance is achieved, in part, by reducing base region resistance and its associated debiasing effect and by minimizing parasitic capacitive effects of the emitter-base junction. As shown in FIG. 1 (prior art), this is often accomplished by providing a lightly doped intrinsic base region and a heavily doped extrinsic base region for each transistor.
Details of a typical process for the fabrication of bipolar transistors can be found in texts on semiconductor fabrication such as Microelectronics Processing and Device Design, R. A. Colclasser, John Wiley & Sons, copyright 1980.
Summarily, a p-type substrate is oxidized on its upper surface and etched to form a mask used for diffusion of a buried collector region. After the diffusion of n-type impurities, the oxide layer is then stripped and an n-type epitaxial silicon layer is grown. Next, a masking layer is deposited and patterned whereby "field oxide" regions are formed. Another mask is then used to allow diffusion of dopants into the epitaxial layer beneath device separation field oxide regions to form p-type regions which will isolate the individual transistors from adjacent components. Slot or oxide isolation also can be used.
Next in a typical fabrication process, a mask layer is deposited and anisotropically etched to expose a surface area of the silicon epitaxial layer. Extrinsic base regions are then formed in the substrate by deep drive-in or implant and deep drive-in processes. The base oxide layers grown over the doped regions enhance diffusion of the extrinsic base regions into the yet to be formed emitter region and deeper into the epitaxial layer, as demonstrated by FIG. 1. At this stage, the mask is removed and the intrinsic base, emitter and collector are formed. These effects result in degradation of the transistor performance. This process requires a thick epitaxial layer because the extrinsic base profile which results is relatively deep and wide.
Shrinkage of a device with such a profile would result in an unacceptably proportioned transistor. One problem is that the extrinsic base profile is too deep and too wide. With current fabrication and photolithography techniques, emitter width after encroachment by the extrinsic base regions, as shown in FIG. 1, is approximately 1.0 to 2.0 microns. Any significant shrinkage would result in an unacceptable emitter width. Such a transistor would be subject to significant reverse injection and two-dimensional beta reduction.
Moreover, it is common for epitaxial layers to have a thickness of approximately 1.5 to 2.5 microns. Current techniques result in an extrinsic base junction depth of approximately 0.5 to 0.7 micron. During epitaxial layer growth, the buried layer diffuses approximately 0.5 to 0.6 micron upward into the epitaxial layer. Collector-to-base breakdown voltages, BV.sub.cbo, for a thinner epitaxial layer would occur at 10-15 volts or less, which could be unacceptable for many applications.
Hence, a process of forming a bipolar transistor with a shallower and narrower extrinsic base is needed.